ARM ARM7TDMI - Table B-2 Scan Chain Number Allocation

Debug in Depth
B-16 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
The least significant bit of the register is scanned in or out first.
The number of the currently selected scan chain is reflected on the SCREG[3:0]
outputs. The TAP controller can be used to drive external scan chains in addition to
those within the ARM7TDMI macrocell. The external scan chain must be assigned a
number and control signals for it can be derived from SCREG[3:0], IR[3:0],
TAPSM[3:0], TCK1, and TCK2. The list of scan chain numbers allocated by ARM are
shown in Table B-2. An external scan chain can take any other number. The serial data
stream to be applied to the external scan chain is made present on SDINBS, the serial
data back from the scan chain must be presented to the TAP controller on the
SDOUTBS input. The scan chain present between SDINBS and SDOUTBS is
connected between TDI and TDO whenever scan chain 3 is selected, or when any of
the unassigned scan chain numbers is selected. If there is more than one external scan
chain, a multiplexor must be built externally to apply the desired scan chain output to
SDOUTBS. The multiplexor can be controlled by decoding SCREG[3:0].
Table B-2 lists the scan chain number allocation.
B.6.5 Scan chains 0, 1, 2, and 3
These enable serial access to the core logic and to the EmbeddedICE-RT logic for
programming purposes. They are described in detail in the following sections.
Scan chain 0 and 1
Purpose Enables access to the processor core for test and debug.
Length Scan chain 0: 113 bits.
Table B-2 Scan chain number allocation
Scan chain
number
Function
0 Macrocell scan test
1Debug
2 EmbeddedICE-RT logic programming
3
a
a. To be implemented by ASIC designer.
External boundary-scan
4Reserved
8Reserved