ARM ARM7TDMI - Exception Priorities; Table 2-5 Exception Priority Order

Programmer’s Model
2-22 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
2.8.10 Exception priorities
When multiple exceptions arise at the same time, a fixed priority system determines the
order in which they are handled. The priority order is listed in Table 2-5.
Some exceptions cannot occur together:
• The undefined instruction and SWI exceptions are mutually exclusive. Each
corresponds to a particular, non-overlapping, decoding of the current instruction.
• When FIQs are enabled, and a Data Abort occurs at the same time as an FIQ, the
ARM7TDMI processor enters the Data Abort handler, and proceeds immediately
to the FIQ vector.
A normal return from the FIQ causes the Data Abort handler to resume execution.
Data Aborts must have higher priority than FIQs to ensure that the transfer error
does not escape detection. You must add the time for this exception entry to the
worst-case FIQ latency calculations in a system that uses aborts to support virtual
memory.
0x00000010 Data Abort Abort Set Unchanged
0x00000014 Reserved Reserved - -
0x00000018 IRQ IRQ Set Unchanged
0x0000001C FIQ FIQ Set Set
Table 2-4 Exception vectors (continued)
Address Exception Mode on entry I state on entry F state on entry
Table 2-5 Exception priority order
Priority Exception
Highest Reset
Data Abort
FIQ
IRQ
Prefetch Abort
Lowest Undefined instruction and SWI