Instruction Cycle Timings
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-21
6.14 Coprocessor data transfer from memory to coprocessor
For coprocessor transfer instructions from memory the coprocessor must commit to the
transfer only when it is ready to accept the data. When CPB goes LOW, the processor
produces the addresses and expects the coprocessor to take the data at sequential cycle
rates. The coprocessor is responsible for determining the number of words to be
transferred, and indicates the last transfer cycle by driving CPA and CPB HIGH.
The ARM7TDMI processor spends the first cycle (and any busy-wait cycles) generating
the transfer address, and updates the base address during the transfer cycles.
The cycle timings are listed in Table 6-17 where:
• b represents the busy cycles
• n represents the number of registers.
Table 6-17 Coprocessor data transfer instruction cycle operations
CP
register
status
Cycles Address
MA
S
[1:0]
nRW Data nMREQ SEQ nOPC nCPI CPA CPB
Single 1 pc+8 2 0 (pc+8) 0 0 0 0 0 0
register 2 alu 2 0 (alu) 0 0 1 1 1 1
ready pc+12
Single 1 pc+8 2 0 (pc+8) 1 0 0 0 0 1
register 2 pc+8 2 0 - 1 0 1 0 0 1
not ready • pc+8 2 0 - 1 0 1 0 0 1
bpc+820-0 01000
b+1 alu 2 0 (alu) 0 0 1 1 1 1
pc+12
n registers 1 pc+8 2 0 (pc+8) 0 0 0 0 0 0
(n>1) 2 alu 2 0 (alu) 0 1 1 1 0 0
ready • alu+• 2 0 (alu+•) 0 1 1 1 0 0
n alu+• 2 0 (alu+•) 0 1 1 1 0 0
n+1 alu+• 2 0 (alu+•) 0 0 1 1 1 1
pc+12
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