Programmer’s Model
2-24 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
2.10 Reset
When the nRESET signal goes LOW a reset occurs, and the ARM7TDMI core
abandons the executing instruction and continues to increment the address bus as if still
fetching word or halfword instructions. nMREQ and SEQ indicates internal cycles
during this time.
When nRESET goes HIGH again, the ARM7TDMI processor:
1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and
CPSR into them. The values of the PC and CPSR are indeterminate.
2. Forces M[4:0] to b10011, Supervisor mode, sets the I and F bits, and clears the
T-bit in the CPSR.
3. Forces the PC to fetch the next instruction from address
0x00
.
4. Reverts to ARM state if necessary and resumes execution.
After reset, all register values except the PC and CPSR are indeterminate.
More information is provided in Reset sequence after power up on page 3-32.
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