ARM ARM7TDMI - Figure 3-4 Internal Cycles; Figure 3-7 Memory Cycle Timing; Figure 3-14 External Connection of Unidirectional Buses

Index
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. Index-3
scan chain 3 B-20
scan chains B-16
scan path select register B-15
stages 5-2
status register B-54
system sppeed access B-32
system state B-24
systems 5-4
target 5-5
test data registers B-14
bypass B-14
ID code B-14
instruction B-15
scan path select B-15
timing 7-12
watchpoint registers B-42
programming and reading B-43
watchpoint with another exception
B-31
watchpoints B-30
programming B-50
Debug Communications Channel. see
DCC
Depipelined address timings 3-15
E
EmbeddedICE
timing B-59
EmbeddedICE-RT 1-3, C-3
disabling 5-16
logic 5-14
registers
function and mapping B-42
ETM7 interface C-4
Exception
timing 7-11
Exception entry/exit summary 2-16
Exception priorities 2-22
Exception vectors 2-21
Exceptions 2-16
abort 2-19
data 2-20
prefetch 2-20
entering 2-17
FIQ 2-18
IRQ 2-19
leaving 2-18
SWI 2-21
undefined instruction 2-21
External bus arrangement 3-17
External connection of unidirectional
buses 3-19
External coprocessors 4-15
F
FIQ mode 2-7
H
Halfword accesses 3-26, 3-27
I
ID code register B-14
Instruction cycle timings
branch 6-4
branch and exchange 6-6
branch with link 6-4
coprocessor absent 6-27
coprocessor data operation 6-20
coprocessor data transfer 6-21
coprocessor register transfer 6-25
data operations 6-7
data swap 6-18
exceptions 6-19
instruction speed summary 6-29
load multiple registers 6-15
load register 6-12
multiply 6-9
multiply accumulate 6-9
store multiple registers 6-17
store register 6-14
SWI 6-19
Thumb branch with link 6-5
undefined instructions 6-27
unexecuted instructions 6-28
Instruction pipeline 1-2, 1-3
Instruction register B-8
Instruction set
ARM 1-5
ARM formats 1-12
summary 1-11
Thumb 1-5, 1-20
Thumb formats 1-21
Thumb summary 1-22
Instruction set formats 1-11
Instruction speed summary 6-29
Instructions
LDC 4-10
STC 4-10
INSTRVALID signal C-4
Internal cycles 3-7
Interrupt disable bits 2-14
Interrupt latencies 2-23
maximum 2-23
minimum 2-23
IRQ mode 2-7
L
LDC 4-10
Link register 2-8
Little-endian 2-4
M
Memory access 1-3
Memory cycle timing
summary 3-10
Memory formats 2-4
big-endian 2-4
little-endian 2-4
Merged I-S cycles 3-8
Mode bits 2-15
Modulating MCLK 3-29
Monitor mode 5-21
N
Nonsequential cycles 3-5
Numerical conventions xix
O
Operating modes 2-7
Operating states 2-3
switching states 2-3