Index
Index-2 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
nonsequential 3-5
sequential 3-6
types, description 3-4
use of nWAIT 3-29
Bus interface
cycle types 3-4
signals 3-3
Byte accesses 3-26, 3-27
C
Clock domains 5-11
Clocks 5-3
Code density 1-6
Condition code flags 2-13
Control bits 2-14
Conventions
numerical xix
signal naming xviii
timing diagram xviii
typographical xvii
Coprocessor
busy-wait sequence 4-8
Coprocessor connections
bidirectional bus 4-12
unidirectional bus 4-13
Coprocessor interface
handshaking 4-6
Coprocessor register cycles 3-9
Coprocessors
about 4-2
absence of external 4-15
availability 4-3
connecting 4-12
connecting multiple 4-13
connecting single 4-12
consequences of busy-waiting 4-8
data operation sequence 4-10
data operations 4-10
external 4-15
interface signals 4-4
load and store operations 4-10
load sequence 4-11
privileged instructions 4-17
register transfer instructions 4-9
register transfer sequence 4-9
signaling 4-7
timing 7-10
undefined instructions 4-16
Core clocks B-22
Core scan chain arrangements B-4
CPA 4-7
CPB 4-7
CPnCPI 4-7
D
Data
multiplexing 4-13
Data Aborts B-34
Data bus control circuit 3-20
Data replication 3-28
Data timed signals 3-17
Data types 2-6
Data write bus cycle 3-20
DCC
access through JTAG C-4
bandwidth improvements C-4
communications through 5-18
interrupt-driven use 5-20
registers 5-17
DCC control register 5-17
Debug
behavior of PC B-30
breakpoints B-30
hardware B-47
programming B-47
software B-48, B-49
bypass register B-14
clock 5-3
clock switch during B-22
clock switch during test 5-12, B-23
clock switching 5-11
communications channel. see DCC
communications through the DCC
5-18
control and status register format
B-55
control register B-51
control registers B-44
core clocks B-22
core state B-24
coupling breakpoints and
watchpoints B-57
determining core state 5-13, B-24
determining system state 5-13, B-26
EmbeddedICE-RT
block diagram B-43
timing B-59
entry into 5-7
on breakpoint 5-8
on debug request 5-9
on watchpoint 5-9
exit sequence B-28
function and mapping of
EmbeddedICE-RT registers
B-42
host 5-4
ID code register B-14
instruction register B-8, B-15
interface 5-2
interface signals 5-7
interrupt-driven use of DCC 5-20
mask registers B-44
messages
receiving from the debugger
5-19
sending to the debugger 5-19
output enable and disable times due
to HIGHZ TAP instruction 7-17,
7-18
priorities and exceptions B-33
Data Aborts B-34
interrupts B-33
Prefetch Abort B-33
protocol converter 5-4
public instructions B-9
BYPASS B-12
CLAMP B-11
CLAMPZ B-11
EXTEST B-9
HIGHZ B-11
IDCODE B-12
INTEST B-12
RESTART B-10
SAMPLE/PRELOAD B-10
SCAN_N B-10
request B-31
reset period timing 7-17
return address calculation B-32
scan chain 0 B-18
scan chain 0 cells B-35
scan chain 1 B-19
scan chain 1 cells B-40
scan chain 2 B-19
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