ARM ARM7TDMI - Page 283

ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. Index-1
Index
A
Abort Mode 2-7
ABORT signal 3-24
AC Timing diagrams 7-2
ABE address control 7-5
ALE address control 7-18
APE address control 7-19
bidirectional data read cycle 7-6
bidirectional data write cycle 7-5
breakpoint timing 7-14
configuration pin timing 7-9
coprocessor timing 7-10
data bus control 7-7
DCC output 7-13
debug timing 7-12
exception timing 7-11
general timings 7-3, 7-4
MCLK 7-15
output 3-state time 7-8
scan general timing 7-16
synchronous interrupt 7-12
TCK and ECLK realtionship 7-14
unidirectional data read cycle 7-9
unidirectional data write cycle 7-8
units of nanoseconds 7-20
Access times, stretching 3-29
Accesses
byte 3-26
halfword 3-26
reads 3-26
writes 3-27
Accessing high registers in Thumb state
2-12
Address bits, significant 3-12
Address bus, configuring 3-14
Address timing 3-14
Addressing signals 3-11
ARM
instruction summary 1-13
ARM-state
addressing modes 1-15
condition fields 1-19
fields 1-19
operand 2 1-18
register organization 2-9
register set 2-8
B
Bidirectional bus timing 3-18
Bidirectional data bus 3-19
Big-endian 2-4, 2-5
Block diagram of ARM7TDMI
processor 1-8
Breakpoints
hardware B-47
programming B-47
software B-48
clearing B-49
setting B-48
timing 7-14
Burst types 3-7
Bus cycles
types
coprocessor register transfer 3-9
internal 3-7
merged I-S 3-8