ARM ARM7TDMI - Chapter 1 Introduction; About the ARM7 TDMI Core; Figure 1-1 Instruction Pipeline

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Introduction

1.1 About the ARM7TDMI core

The ARM7TDMI core is a member of the ARM family of general-purpose 32-bit

microprocessors. The ARM family offers high performance for very low power

consumption, and small size.

The ARM architecture is based on Reduced Instruction Set Computer (RISC)

principles. The RISC instruction set and related decode mechanism are much simpler

than those of Complex Instruction Set Computer (CISC) designs. This simplicity gives:

• a high instruction throughput

• an excellent real-time interrupt response

• a small, cost-effective, processor macrocell.

This section describes:

• The instruction pipeline

• Memory access on page 1-3

• Memory interface on page 1-3.

• EmbeddedICE-RT logic on page 1-3.

1.1.1 The instruction pipeline

The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions

to the processor. This enables several operations to take place simultaneously, and the

processing and memory systems to operate continuously.

A three-stage pipeline is used, so instructions are executed in three stages:

• Fetch

• Decode

• Execute.

The instruction pipeline is shown in Figure 1-1.

Figure 1-1 Instruction pipeline

Fetch

Decode

Execute

Instruction fetched from memory

Decoding of registers used in

instruction

Shift and ALU operation

Write register(s) back to register bank

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