Instruction Cycle Timings
6-12 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
6.7 Load register
The first cycle of a load register instruction performs the address calculation. During the
second cycle the data is fetched from memory and the base register modification is
performed, if required. During the third cycle the data is transferred to the destination
register, and external memory is unused. This third cycle can normally be merged with
the next prefetch cycle to form one memory N-cycle.
Either the base, or destination, or both, can be the PC, and the prefetch sequence is
changed if the PC is affected by the instruction.
The data fetch can abort, and in this case the destination modification is prevented. In
addition, if the processor is configured for early abort, the base register write-back is
also prevented.
The cycle timings are listed in Table 6-9 where:
• c represents the current processor mode:
—c=0 for User mode
— c=1 for all other modes
• d=0 if the T bit has been specified in the instruction (such as LDRT) and d=c at
all other times
• s represents the size of the data transfer shown by MAS[1:0] (see Table 6-10 on
page 6-13).
Table 6-9 Load register instruction cycle operations
Operation type Cycle Address MAS[1:0] nRW Data nMREQ SEQ nOPC nTRANS
normal 1 pc+2L i 0 (pc+2L) 0 0 0 c
2alu s 0(alu)1 01 d
3 pc+3L i 0 - 0 1 1 c
pc+3L
dest=pc 1 pc+8 2 0 (pc+8) 0 0 0 c
2alu 0pc’1 01d
3 pc+12 2 0 - 0 0 1 c
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