ARM ARM7TDMI User Manual

Memory Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-3
3.2 Bus interface signals
The signals in the ARM7TDMI processor bus interface can be grouped into four
categories:
• clocking and clock control
• address class signals
• memory request signals
• data timed signals.
The clocking and clock control signals are:
• MCLK
• nWAIT
• ECLK
• nRESET.
The address class signals are:
• A[31:0]
• nRW
• MAS[1:0]
• nOPC
• nTRANS
• LOCK
• TBIT.
The memory request signals are:
• nMREQ
• SEQ.
The data timed signals are:
• D[31:0]
• DIN[31:0]
• DOUT[31:0]
• ABORT
• BL[3:0].
The ARM7TDMI processor uses both the rising and falling edges of MCLK.
Bus cycles can be extended using the nWAIT signal. This signal is described in
Stretching access times on page 3-29. All other sections of this chapter describe a
simple system in which nWAIT is permanently HIGH.

ARM ARM7TDMI Specifications

General

Brand	ARM
Model	ARM7TDMI
Category	Computer Hardware
Language	English