ARM ARM7TDMI - Table 7-21 ALE Address Control Timing Parameters; Table 7-22 APE Address Control Timing Parameters; Figure 7-23 APE Address Control

AC and DC Parameters
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-19
Note
In Figure 7-22 on page 7-18, T
ald
is the time by which ALE must be driven LOW to
latch the current address in phase 2. If ALE is driven LOW after T
ald
, then a new address
is latched. This is known as address breakthrough.
The timing parameters used in Figure 7-22 on page 7-18 are listed in Table 7-21.
Figure 7-23 APE address control
The timing parameters used in Figure 7-23 are listed in Table 7-22.
Table 7-21 ALE address control timing parameters
Symbol Parameter
Parameter
type
T
ald
Address group latch output time Maximum
T
ale
Address group latch open output delay Maximum
T
aleh
Address group latch output hold time Minimum
MCLK
T
aph
A[31:0]
nRW
LOCK
nOPC
nTRANS
MAS[1:0]
T
aps
APE
T
ape
T
apeh
Table 7-22 APE address control timing parameters
Symbol Parameter
Parameter
type
T
ape
MCLKf to address group valid Maximum
T
apeh
Address group output hold time from MCLKf Minimum
T
aph
APE hold time from MCLKf Minimum
T
aps
APE set up time to MCLKr Minimum