ARM ARM7TDMI - Table 7-5 Data Bus Control Timing Parameters; Figure 7-5 Data Bus Control

AC and DC Parameters
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-7
Figure 7-5 Data bus control
Note
The cycle shown in Figure 7-5 is a data write cycle because nENOUT was driven LOW
during phase one. Here, DBE has first been used to modify the behavior of the data bus,
and then nENIN.
The timing parameters used in Figure 7-5 are listed in Table 7-5.
T
dbz
nENOUT
DBE
T
dbnen
D[31:0]
T
dout
T
dbe
T
dbnen
T
doh
nENIN
T
dbz
T
dbe
MCLK
Table 7-5 Data bus control timing parameters
Symbol Parameter Parameter type
T
dbe
Data bus enable time from DBErMaximum
T
dbnen
DBE to nENOUT valid Maximum
T
dbz
Data bus disable time from DBEfMaximum
T
doh
DOUT[31:0] hold from MCLKfMinimum
T
dout
MCLKf to D[31:0] valid Maximum