Need help?Do you have a question about the ARM Cortex-A35 and is the answer not in the manual?
General| Brand | ARM |
|---|---|
| Model | Cortex-A35 |
| Category | Computer Hardware |
| Language | English |
This Technical Reference Manual is for the Cortex -A35 processor. It provides reference documentation and contains programming details for registers.
Contact your supplier and give the product name, revision or version, and an explanation.
This chapter provides an overview of the Cortex -A35 processor and its features.
This chapter describes the structure of the Cortex -A35 processor.
This chapter describes the clocks of the Cortex -A35 processor. It also describes the reset options.
This chapter describes the power domains and the power modes in the Cortex -A35 processor.
This chapter describes the CPU and SCU cache protection features of the Cortex -A35 processor.
This chapter describes the L1 instruction cache and data cache.
This chapter describes the L2 memory system and the Snoop Control Unit (SCU) that is tightly integrated with it.
This chapter describes the AXI master memory interface.
This chapter describes the ACE master interface.
This chapter describes the CHI master memory interface.
This chapter describes the ACP slave interface.
This chapter describes the Generic Interrupt Controller (GIC) CPU interface of the processor.
This chapter describes the system registers in the AArch32 state.
This chapter describes the system registers in the AArch64 state.
This chapter describes the GIC registers.
This chapter describes the Generic Timer registers.
This chapter describes the debug features of the processor.
This chapter describes the Performance Monitor Unit (PMU) of the processor.
This chapter describes the Embedded Trace Macrocell (ETM) of the processor.
This chapter describes the cross-trigger components of the processor.
This chapter describes the direct access to internal memory that caches and TLBs use.
This chapter describes the debug registers in the AArch32 execution state and shows examples of how to use them.
This chapter describes the debug registers in the AArch64 execution state and shows examples of how to use them.
This chapter describes the debug memory-mapped registers and shows examples of how to use them.
This chapter describes the ROM table that debuggers can use to determine which components are implemented. It also describes the ROM table registers.
This chapter describes the PMU registers.
This chapter describes the ETM registers.
This chapter describes the CTI registers.
This appendix describes the signals at the external interfaces of the processor.
The cases in which the Cortex -A35 processor implementation diverges from the preferred behavior described in Armv8 AArch32 UNPREDICTABLE behaviors.
This appendix describes the technical changes between released issues of this book.
To Next Page
