B1.84 Processor Feature Register 0
The ID_PFR0 characteristics are:
Purpose
Gives top-level information about the instruction sets supported by the processor in AArch32.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
ID_PFR0 must be interpreted with ID_PFR1.
Configurations
ID_PFR0 is architecturally mapped to AArch64 register ID_PFR0_EL1. See B2.67 AArch32
Processor Feature Register 0, EL1 on page B2-475.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_PFR0 is a 32-bit register.
31
12 11 8 7 0
RES0 State2 State1
16 15 4 3
State0State3
Figure B1-39 ID_PFR0 bit assignments
[31:16]
Reserved, RES0.
State3, [15:12]
Indicates support for Thumb Execution Environment (T32EE) instruction set. This value is:
0x0 Processor does not support the T32EE instruction set.
State2, [11:8]
Indicates support for Jazelle. This value is:
0x1 Processor supports trivial implementation of Jazelle.
State1, [7:4]
Indicates support for T32 instruction set. This value is:
0x3 Processor supports T32 encoding after the introduction of Thumb-2 technology, and
for all 16-bit and 32-bit T32 basic instructions.
State0, [3:0]
Indicates support for A32 instruction set. This value is:
0x1 A32 instruction set implemented.
To access the ID_PFR0:
MRC p15,0,<Rt>,c0,c1,0 ; Read ID_PFR0 into Rt
B1 AArch32 system registers
B1.84 Processor Feature Register 0
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B1-289
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