0x2 Cache, TLB and branch predictor operations affect structures according to shareability
and defined behavior of instructions.
BPMaint, [11:8]
Branch predictor maintenance. Indicates the supported branch predictor maintenance operations.
0x2 Supported branch predictor maintenance operations are:
• Invalidate all branch predictors.
• Invalidate branch predictors by MVA.
CMaintSW, [7:4]
Cache maintenance by set/way. Indicates the supported cache maintenance operations by set/
way.
0x1 Supported hierarchical cache maintenance operations by set/way are:
• Invalidate data cache by set/way.
• Clean data cache by set/way.
• Clean and invalidate data cache by set/way.
CMaintVA, [3:0]
Cache maintenance by MVA. Indicates the supported cache maintenance operations by MVA.
0x1 Supported hierarchical cache maintenance operations by MVA are:
• Invalidate data cache by MVA.
Invalidate data cache by MVA operations are treated as clean and invalidate data
cache by MVA operations on the executing core. If the operation is broadcast to
another core then it is broadcast as an invalidate data cache by MVA operation.
• Clean data cache by MVA.
• Clean and invalidate data cache by MVA.
• Invalidate instruction cache by MVA.
• Invalidate all instruction cache entries.
To access the ID_MMFR3:
MRC p15, 0, <Rt>, c0, c1, 7; Read ID_MMFR3 into Rt
Register access is encoded as follows:
Table B1-66 ID_MMFR3 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0001 111
B1 AArch32 system registers
B1.83 Memory Model Feature Register 3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-288
Non-Confidential
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