ARM Cortex-A35

C11.58 Device Affinity Register 1
The TRCDEVAFF1 characteristics are:
Purpose
The value is a read-only copy of MPIDR_EL1[63:32] as seen from EL3, unaffected by
VMPIDR_EL2.
Usage constraints
Accessible only from the external debug interface.
Configurations
Available in all configurations.
Attributes
TRCDEVAFF1 is a 32-bit RO management register.
For the Cortex‑A35 processor, MPIDR_EL1[63:32] is RES0.
See C11.1 ETM register summary on page C11-733.
The TRCDEVAFF1 can be accessed through the external debug interface, offset 0xFAC.
C11 ETM registers
C11.58 Device Affinity Register 1
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C11-806
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