ARM Cortex-A35 User Manual

B2.59 AArch32 Instruction Set Attribute Register 2, EL1
The ID_ISAR2_EL1 characteristics are:
Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_ISAR2_EL1 is architecturally mapped to AArch32 register ID_ISAR2. See
B1.76 Instruction Set Attribute Register 2 on page B1-273.
Attributes
ID_ISAR2_EL1 is a 32-bit register.
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
MultiAccessInt
Reversal PSR_AR MultU MultS Mult MemHint LoadStore
Figure B2-32 ID_ISAR2_EL1 bit assignments
Reversal, [31:28]
Indicates the implemented Reversal instructions:
0x2 The REV, REV16, REVSH, and RBIT instructions.
PSR_AR, [27:24]
Indicates the implemented A and R profile instructions to manipulate the PSR:
0x1 The MRS and MSR instructions, and the exception return forms of data-processing
instructions.
The exception return forms of the data-processing instructions are:
• In the A32 instruction set, data-processing instructions with the PC as the destination and the
S bit set.
• In the T32 instruction set, the SUBS PC, LR, #N instruction.
MultU, [23:20]
Indicates the implemented advanced unsigned Multiply instructions:
0x2 The UMULL, UMLAL and UMAAL instructions.
MultS, [19:16]
Indicates the implemented advanced signed Multiply instructions.
B2 AArch64 system registers
B2.59 AArch32 Instruction Set Attribute Register 2, EL1
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English