C2.2 External register access permissions to the PMU registers
External access permission to the PMU registers is subject to conditions at the time of the access.
The following table describes the processor response to accesses through the external debug interface.
Table C2-1 Conditions on external register access to PMU
Name Condition Description
Off EDPRSR.PU is 0
Processor power domain is completely off or in a low-power state where the
processor power domain registers cannot be accessed.
DLK EDPRSR.DLK is 1 OS Double Lock is locked.
OSLK OSLSR_EL1.OSLK is 1 OS Lock is locked.
EPMAD
AllowExternalPMUAccess() == FALSE
External performance monitors access is disabled. When an error is returned
because of an EPMAD condition code, and it is the highest priority error
condition, EDPRSR.SPMAD is set to 1. Otherwise SPMAD is unchanged.
SLK Memory-mapped interface only Software lock is locked. For the external debug interface, ignore this column.
Default - None of the conditions apply, normal access.
To determine the access permission for the register, scan the columns from left to right in the register
usage constraints table. An example is shown in Table C2-2 Example for external register condition
code on page C2-587 . Stop at the first column in which the condition is true. The entry gives the
register access permission and scanning stops.
Table C2-2 Example for external register condition code
Off DLK OSLK EPMAD SLK Default
- - - - RO/WI RO
C2 PMU
C2.2 External register access permissions to the PMU registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C2-587
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