ARM Cortex-A35 User Manual

B2.18 AArch64 Implementation defined registers
IMPLEMENTATION DEFINED registers provide test features and any required configuration options specific to
the Cortex‑A35 processor.
The following table shows the IMPLEMENTATION DEFINED registers in AArch64 state. If a register is not
indicated as mapped to an AArch32 64-bit register, bits[63:32] are 0x00000000.
Table B2-17 AArch64 implementation defined registers
Name Type Reset Width Description
ACTLR_EL1 RW
0x00000000
32 B2.19 Auxiliary Control Register, EL1 on page B2-386
ACTLR_EL2 RW
0x00000000
32 B2.20 Auxiliary Control Register, EL2 on page B2-387
ACTLR_EL3 RW
0x00000000
32 B2.21 Auxiliary Control Register, EL3 on page B2-389
AFSR0_EL1 RW
0x00000000
32 B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3
on page B2-391
AFSR1_EL1 RW
0x00000000
32 B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3
on page B2-392
AFSR0_EL2 RW
0x00000000
32 B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3
on page B2-391
AFSR1_EL2 RW
0x00000000
32 B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3
on page B2-392
AFSR0_EL3 RW
0x00000000
32 B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3
on page B2-391
AFSR1_EL3 RW
0x00000000
32 B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3
on page B2-392
AMAIR_EL1 RW
0x0000000000000000
64 B2.25 Auxiliary Memory Attribute Indirection Register, EL1
on page B2-394
AMAIR_EL2 RW
0x0000000000000000
64 B2.26 Auxiliary Memory Attribute Indirection Register, EL2
on page B2-395
AMAIR_EL3 RW
0x0000000000000000
64 B2.27 Auxiliary Memory Attribute Indirection Register, EL3
on page B2-396
L2CTLR_EL1 RW
-
32
B2.74 L2 Control Register, EL1 on page B2-489
The reset value depends on the processor implementation and the
state of the L2RSTDISABLE signal.
L2ECTLR_EL1 RW
0x00000000
32
B2.75 L2 Extended Control Register, EL1 on page B2-491
L2ACTLR_EL1 RW
0x80000000
32
B2.73 L2 Auxiliary Control Register, EL1 on page B2-486
This is the reset value for an ACE interface. For an AXI interface the
reset value is 0x 80000008. For a CHI interface the reset value is
0x80004008.
CPUACTLR_EL1 RW
0x00000000090CA000
64
B2.36 CPU Auxiliary Control Register, EL1 on page B2-412
Mapped to a 64-bit AArch32 register.
B2 AArch64 system registers
B2.18 AArch64 Implementation defined registers
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B2-384
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English