B1.102 Revision ID Register
The REVIDR characteristics are:
Purpose
Provides implementation-specific minor revision information that can be interpreted only in
conjunction with the Main ID Register.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Configurations
REVIDR is architecturally mapped to AArch64 register REVIDR_EL1. See B2.86 Revision ID
Register, EL1 on page B2-518.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
REVIDR is a 32-bit register.
31
0
ID number
Figure B1-55 REVIDR bit assignments
ID number, [31:0]
Implementation-specific revision information. The reset value is determined by the specific
Cortex‑A35 processor implementation.
0x00000000 Revision code is zero.
To access the REVIDR:
MRC p15, 0, <Rt>, c0, c0, 6; Read REVIDR into Rt
Register access is encoded as follows:
Table B1-87 REVIDR access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0000 110
B1 AArch32 system registers
B1.102 Revision ID Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-325
Non-Confidential
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