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ARM Cortex-A35 User Manual

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B1.49 Data Fault Status Register
The DFSR characteristics are:
Purpose
Holds status information about the last data fault.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
Configurations
DFSR (NS) is architecturally mapped to AArch64 register ESR_EL1. See B2.41 Exception
Syndrome Register, EL1 on page B2-423
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
There are two formats for this register. The current translation table format determines which
format of the register is used.
Attributes
DFSR is a 32-bit register.
B1 AArch32 system registers
B1.49 Data Fault Status Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-223
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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