B2.94 Translation Control Register, EL1
The TCR_EL1 characteristics are:
Purpose
Determines which Translation Base Registers defines the base address register for a translation
table walk required for stage 1 translation of a memory access from EL0 or EL1 and holds
cacheability and shareability information.
TCR_EL1 is part of the Virtual memory control registers functional group.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
Configurations
TCR_EL1 is architecturally mapped to AArch32 register TTBCR(NS). See B1.110 Translation
Table Base Control Register on page B1-341.
Attributes
TCR_EL1 is a 64-bit register.
RES0
RES0
IPS
TBI1
TBI0
AS
063
T0SZ
RES0
6 58 711 10 9
SH0TG0
1216 15 14 13
EPD0
IRGN0
ORGN0
T1SZ
26 25 24 23 22
IRGN1
A1
EPD1
ORGN1
2731 30 29 28
TG1 SH1
323438 37 36 3539 21
Figure B2-65 TCR_EL1 bit assignments
[63:39]
Reserved, RES0.
TBI1, [38]
Top Byte Ignored. Indicates whether the top byte of the input address is used for address match
for the TTBR1_EL1 region. The possible values are:
0 Top byte used in the address calculation.
1 Top byte ignored in the address calculation.
TBI0, [37]
Top Byte Ignored. Indicates whether the top byte of the input address is used for address match
for the TTBR0_EL1 region. The possible values are:
0 Top byte used in the address calculation.
1 Top byte ignored in the address calculation.
AS, [36]
ASID size. The possible values are:
B2 AArch64 system registers
B2.94 Translation Control Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-536
Non-Confidential
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