ARM Cortex-A35 User Manual

C5.6 Encoding for IPA cache
The following table shows the data fields in the IPA cache descriptor.
Table C5-12 IPA cache descriptor fields
Bits Name Description
[115:113] Parity bits If CPU cache protection is not implemented, these bits are absent.
[112:85] PA Physical address.
[84:62] IPA Unused lower bits, page size dependent, must be zero.
[61:59] - Reserved, must be zero.
[58:55] Size
Stage 2 page size. The values are:
0b0001
4KB.
0b1001
16KB.
0b0011
64KB.
0b0101
2MB.
0b1011
32MB.
0b0111
512MB.
[54:39] - Reserved, must be zero.
[38:31] VMID Virtual Machine Identifier.
[30:12] - Reserved, must be zero.
[11:10] Entry granule
The values are:
0b00
4KB.
0b10
16KB.
0b01
64KB.
[9:6] Memattrs Memory attributes.
[5] XN Execute Never.
[4:3] HAP Hypervisor access permissions.
[2:1] SH Shareability.
[0] Valid The entry contains valid data.
C5 Direct access to internal memory
C5.6 Encoding for IPA cache
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C5-618
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English