C11.44 Power Down Status Register
The TRCPDSR characteristics are:
Purpose
Indicates the power down status of the ETM trace unit.
Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes
See C11.1 ETM register summary on page C11-733.
RES0RES0
31 6 5 4 2 1 0
OSLK
STICKYPD
POWER
Figure C11-43 TRCPDSR bit assignments
[31:6]
Reserved, RES0.
OSLK, [5]
OS lock status.
0 The OS Lock is unlocked.
1 The OS Lock is locked.
[4:2]
Reserved, RES0.
STICKYPD, [1]
Sticky power down state.
0 Trace register power has not been removed since the TRCPDSR was last read.
1 Trace register power has been removed since the TRCPDSR was last read.
This bit is set to 1 when power to the ETM trace unit registers is removed, to indicate that
programming state has been lost. It is cleared after a read of the TRCPDSR.
POWER, [0]
Indicates the ETM trace unit is powered:
0 ETM trace unit is not powered. The trace registers are not accessible and they all
return an error response.
1 ETM trace unit is powered. All registers are accessible.
If a system implementation allows the ETM trace unit to be powered off independently of the
debug power domain, the system must handle accesses to the ETM trace unit appropriately.
The TRCPDSR can be accessed through the external debug interface, offset 0x314.
C11 ETM registers
C11.44 Power Down Status Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C11-790
Non-Confidential
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