B2.84 Multiprocessor Affinity Register, EL1
The MPIDR_EL1 characteristics are:
Purpose
Provides an additional core identification mechanism for scheduling purposes in a cluster
system.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
MPIDR_EL1[31:0] is:
• Architecturally mapped to AArch32 register MPIDR. See B1.97 Multiprocessor Affinity
Register on page B1-315.
• Mapped to external register EDDEVAFF0.
MPIDR_EL1[63:32] is:
• Mapped to external register EDDEVAFF1.
Attributes
MPIDR_EL1 is a 64-bit register.
Aff1 Aff0
063 16 15
8 7
Aff2
2324
MT
RES0
2930
U
32 31
Aff3
40 39
RES0
RES1
25
Figure B2-54 MPIDR_EL1 bit assignments
[63:40]
Reserved, RES0.
Aff3, [39:32]
Affinity level 3. Highest level affinity field.
Reserved, RES0.
[31]
Reserved, RES1.
U, [30]
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
0 Processor is part of a multiprocessor system. This is the value for implementations
with more than one core, and for implementations with an ACE or CHI master
interface.
1 Processor is part of a uniprocessor system. This is the value for single core
implementations with an AXI master interface.
B2 AArch64 system registers
B2.84 Multiprocessor Affinity Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-512
Non-Confidential
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