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ARM Cortex-A35 User Manual

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C12.6 CTI Peripheral Identification Register 0
The CTIPIDR0 characteristics are:
Purpose
Provides information to identify a CTI component.
Usage constraints
The accessibility of CTIPIDR0 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
C12.2 External register access permissions to the CTI registers on page C12-828 describes the
condition codes.
Configurations
CTIPIDR0 is in the Debug power domain.
CTIPIDR0 is optional to implement in the external register interface.
Attributes
See the register summary in C12.1 Cross trigger register summary on page C12-826.
RES0
31 0
78
Part_0
Figure C12-3 CTIPIDR0 bit assignments
[31:8]
Reserved, RES0.
Part_0, [7:0]
0xDA Least significant byte of the cross trigger part number.
CTIPIDR0 can be accessed through the external debug interface, offset 0xFE0.
C12 CTI registers
C12.6 CTI Peripheral Identification Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C12-833
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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