ARM Cortex-A35 User Manual

B2.90 System Control Register, EL1
The SCTLR_EL1 characteristics are:
Purpose
Provides top level control of the system, including its memory system at EL1.
SCTLR_EL1 is part of the Virtual memory control registers functional group.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
Configurations
SCTLR_EL1 is architecturally mapped to AArch32 register SCTLR(NS) See B1.105 System
Control Register on page B1-331.
Attributes
SCTLR_EL1 is a 32-bit register.
31 0
MACIRES0
SA
CP15BEN
ITD
SED
UMA
SA0
RES0
RES0
EE
DZE
nTWI
RES0
UCT
E0E
UCI
THEE
2526 24 23 20 1819 17 16 15 1314 12 11 10 89 7 6 5 34 2 127282930
RES1
RES0
2122
RES1
RES0
RES1
WXN
nTWE
RES1
Figure B2-61 SCTLR_EL1 bit assignments
[31:30]
Reserved, RES0.
[29:28]
Reserved, RES1.
[27]
Reserved, RES0.
UCI, [26]
Enables EL0 access to the DC CVAU, DC CIVAC, DC CVAC and IC IVAU instructions in the
AArch64 Execution state. The possible values are:
0 EL0 access disabled. This is the reset value.
1 EL0 access enabled.
EE, [25]
B2 AArch64 system registers
B2.90 System Control Register, EL1
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reserved.
B2-525
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English