B2.89 Secure Configuration Register, EL3
The SCR_EL3 characteristics are:
Purpose
Defines the configuration of the security state. SCR_EL3 specifies:
• Security state of EL0 and EL1, either Secure or Non-secure.
• Register width at lower exception levels.
• The exception level that the processor takes exceptions at, if an IRQ, FIQ, or external abort
occurs.
SCR_EL3 is part of the Security registers functional group.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW
Configurations
SCR_EL3 is mapped to AArch32 register SCR. See B1.104 Secure Configuration Register
on page B1-328.
Attributes
SCR_EL3 is a 32-bit register.
31 10 9 8 7 6 4 3 2 1 0
RES0
SIF
HCE
RW
ST
EA
FIQ
IRQ
NS
RES0
TWI
TWE
11121314
SMD
RES1
5
Figure B2-60 SCR_EL3 bit assignments
[31:14]
Reserved, RES0.
TWE, [13]
Traps WFE instructions. The possible values are:
0 WFE instructions are not trapped. This is the reset value.
B2 AArch64 system registers
B2.89 Secure Configuration Register, EL3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-522
Non-Confidential
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