ARM Cortex-A35

B1.24 AArch32 Address registers
The following table shows the address translation register and operations.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information.
Table B1-23 Address translation operations
Name CRn Op1 CRm Op2 Reset Width Description
PAR c7 0 c4 0
UNK 32-bit
B1.100 Physical Address Register on page B1-321
- 0 c7 - 64-bit
B1 AArch32 system registers
B1.24 AArch32 Address registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-181
Non-Confidential