ARM Cortex-A35 User Manual

B4.2 AArch32 Generic Timer register summary
The following table shows the AArch32 Generic Timer registers.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for information
about these registers.
Table B4-1 AArch32 Generic Timer registers
Name CRn Op1 CRm Op2 Reset Width Description
CNTFRQ c14 0 c0 0 UNK 32-bit
Counter-timer Frequency register
CNTPCT - 0 c14 - UNK 64-bit Counter-timer Physical Count register
CNTKCTL c14 0 c1 0 - 32-bit
Counter-timer Kernel Control register
The reset value for bits[9:8, 2:0] is 0b00000.
CNTP_TVAL c2 0 UNK 32-bit Counter-timer Physical Timer TimerValue register
CNTP_CTL 1
-
32-bit
Counter-timer Physical Timer Control register
The reset value for bit[0] is 0.
CNTV_TVAL c3 0 UNK 32-bit
Counter-timer Virtual Timer TimerValue register
CNTV_CTL 1 32-bit
Counter-timer Virtual Timer Control register
The reset value for bit[0] is 0.
CNTVCT - 1 c14 - UNK 64-bit
Counter-timer Virtual Count register
CNTP_CVAL 2 UNK 64-bit Counter-timer Physical Timer CompareValue register
CNTV_CVAL 3 UNK 64-bit Counter-timer Virtual Timer CompareValue register
CNTVOFF 4 UNK 64-bit
Counter-timer Virtual Offset register
CNTHCTL c14 4 c1 0
-
32-bit
Counter-timer Hyp Control register
The reset value for bit[2] is 0 and for bits[1:0] is 0b11.
CNTHP_TVAL c2 0 UNK 32-bit
Counter-timer Hyp Physical Timer TimerValue register
CNTHP_CTL 1 32-bit
Counter-timer Hyp Physical Timer Control register
The reset value for bit[0] is 0.
CNTHP_CVAL - 6 c14 - UNK 64-bit
Counter-timer Hyp Physical CompareValue register
B4 Generic Timer registers
B4.2 AArch32 Generic Timer register summary
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B4-571
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English