B1.40 Cache Level ID Register
The CLIDR characteristics are:
Purpose
Identifies:
• The type of cache, or caches, implemented at each level.
• The Level of Coherency and Level of Unification for the cache hierarchy.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Configurations
CLIDR is architecturally mapped to AArch64 register CLIDR_EL1. See B2.30 Cache Level ID
Register, EL1 on page B2-400.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
CLIDR is a 32-bit register.
LoUIS
ICB
Ctype3 Ctype2 Ctype1
31 30 29 27 26 24 23 21 20 9 8 6 5 3 2 0
LoUU LoC
RES0
Figure B1-4 CLIDR bit assignments
ICB, [31:30]
Inner cache boundary. This field indicates the boundary between the inner and the outer domain.
0b00 Not disclosed in this mechanism.
LoUU, [29:27]
Indicates the Level of Unification Uniprocessor for the cache hierarchy:
0b001 L1 cache is the last level of cache that must be cleaned or invalidated when cleaning or
invalidating to the point of unification for the processor.
LoC, [26:24]
Indicates the Level of Coherency for the cache hierarchy:
0b001 L2 cache not implemented.
0b010 A clean to the point of coherency operation requires the L1 and L2 caches to be
cleaned.
LoUIS, [23:21]
Indicates the Level of Unification Inner Shareable for the cache hierarchy:
B1 AArch32 system registers
B1.40 Cache Level ID Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-204
Non-Confidential
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