ARM Cortex-A35 User Manual

B1.39 Cache Size ID Register
The CCSIDR characteristics are:
Purpose
Provides information about the architecture of the caches.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
If CSSELR indicates a cache that is not implemented, then on a read of the CCSIDR the
behavior is CONSTRAINED UNPREDICTABLE, and can be one of the following:
• The CCSIDR read is treated as NOP.
• The CCSIDR read is UNDEFINED.
• The CCSIDR read returns an UNKNOWN value (preferred).
Configurations
CCSIDR is architecturally mapped to AArch64 register CCSIDR_EL1. See B2.29 Cache Size
ID Register, EL1 on page B2-398.
There is one copy of this register that is used in both Secure and Non-secure states.
The implementation includes one CCSIDR for each cache that it can access. CSSELR selects
which Cache Size ID Register is accessible.
Attributes
CCSIDR is a 32-bit register.
WB
31 28 27 12 3 0
RA
LineSizeWT
30 29 13 2
WA
NumSets Associativity
Figure B1-3 CCSIDR bit assignments
WT, [31]
Indicates support for Write-Through:
0 Cache level does not support Write-Through.
WB, [30]
Indicates support for Write-Back:
0 Cache level does not support Write-Back.
1 Cache level supports Write-Back.
RA, [29]
Indicates support for Read-Allocation:
0 Cache level does not support Read-Allocation.
1 Cache level supports Read-Allocation.
B1 AArch32 system registers
B1.39 Cache Size ID Register
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B1-201
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English