B1.48 Data Fault Address Register
The DFAR characteristics are:
Purpose
Holds the virtual address of the faulting address that caused a synchronous Data Abort
exception.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
DFAR(S) - - - RW - - RW
DFAR(NS) - - RW - RW RW -
Configurations
DFAR (NS) is architecturally mapped to AArch64 register FAR_EL1[31:0]. See B2.44 Fault
Address Register, EL1 on page B2-429.
DFAR (S) is architecturally mapped to AArch32 register HDFAR. See B1.64 Hyp Data Fault
Address Register on page B1-251.
DFAR (S) is architecturally mapped to AArch64 register FAR_EL2[31:0]. See B2.45 Fault
Address Register, EL2 on page B2-430.
Attributes
DFAR is a 32-bit register.
31
0
VA of faulting address of synchronous Data Abort exception
Figure B1-12 DFAR bit assignments
VA, [31:0]
The Virtual Address of faulting address of synchronous Data Abort exception.
To access the DFAR:
MRC p15, 0, <Rt>, c6, c0, 0 ; Read DFAR into Rt
MCR p15, 0, <Rt>, c6, c0, 0 ; Write Rt to DFAR
Register access is encoded as follows:
Table B1-42 DFAR access encoding
coproc opc1 CRn CRm opc2
1111 000 0110 0000 000
B1 AArch32 system registers
B1.48 Data Fault Address Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-222
Non-Confidential
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