ARM Cortex-A35 User Manual

B2.32 Architectural Feature Trap Register, EL2
The CPTR_EL2 characteristics are:
Purpose
Controls trapping to EL2 for accesses to CPACR, Trace functionality and registers associated
with Advanced SIMD and floating-point execution. Controls EL2 access to this functionality.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
CPTR_EL2 is architecturally mapped to AArch32 register HCPTR. See B1.60 Hyp
Architectural Feature Trap Register on page B1-237.
Attributes
CPTR_EL2 is a 32-bit register.
31 0
RES0 RES1
TFPTCPAC
20 1921 10 911
RES0
TTA
13 1214
RES1
RES0
30
Figure B2-7 CPTR_EL2 bit assignments
TCPAC, [31]
Traps direct access to CPACR from Non-secure EL1 to EL2. The possible values are:
0 Access to CPACR is not trapped. This is the reset value.
1 Access to CPACR is trapped.
[30:21]
Reserved, RES0.
TTA, [20]
Trap Trace Access.
Not implemented. RES0.
[19:14]
Reserved, RES0.
[13:12]
Reserved, RES1.
[11]
Reserved, RES0.
TFP, [10]
Traps instructions that access registers associated with Advanced SIMD and floating-point
execution from a lower exception level to EL2, unless trapped to EL1. The possible values are:
B2 AArch64 system registers
B2.32 Architectural Feature Trap Register, EL2
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B2-404
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English