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ARM Cortex-A35 User Manual

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B1.96 Main ID Register
The MIDR characteristics are:
Purpose
Provides identification information for the processor, including an implementer code for the
device and a device ID number.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Configurations
MIDR is:
Architecturally mapped to the AArch64 MIDR_EL1 register. See B2.83 Main ID Register,
EL1 on page B2-510.
Architecturally mapped to external MIDR_EL1 register.
Attributes
MIDR is a 32-bit register.
VariantImplementer
31 23 20 19 16 15 4 3 0
Architecture PartNum Revision
24
Figure B1-50 MIDR bit assignments
Implementer, [31:24]
Indicates the implementer code. This value is:
0x41 Arm.
Variant, [23:20]
Indicates the variant number of the processor. This is the major revision number n in the rn part
of the rnpn description of the product revision status. This value is:
0x1 r1p0.
Architecture, [19:16]
Indicates the architecture code. This value is:
0xF Defined in the CPUID scheme.
PartNum, [15:4]
Indicates the primary part number. This value is:
0xD04 CortexA35 processor.
Revision, [3:0]
Indicates the minor revision number of the processor. This is the minor revision number n in the
pn part of the rnpn description of the product revision status. This value is:
0x0 r1p0.
B1 AArch32 system registers
B1.96 Main ID Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-313
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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