A1.3 Implementation options
The Cortex‑A35 processor is highly configurable. Build-time configuration options make it possible to
meet functional requirements with the smallest possible area and power.
In a configuration with more than one core, Advanced SIMD and floating-point support can be
implemented on all cores, zero cores, or a subset of cores. If the Cryptographic Extension is included, it
is included on all cores that implement Advanced SIMD and floating-point support. All cores have the
same build-time configuration for other features.
The following table lists the implementation options for a core.
Table A1-1 Implementation options for a core
Feature Range of options Notes
L1 instruction cache size • 8K
• 16K
• 32K
• 64K
L1 data cache size • 8K
• 16K
• 32K
• 64K
CPU cache protection • Included
• Not included
• Not available if the L2 cache is implemented without SCU-L2 cache
protection.
• Also protects the L1 duplicate tags in the SCU.
GIC CPU interface • Included
• Not included
ETM • Included
• Not included
Advanced SIMD and floating-point
support
• Included
• Not included
Advanced SIMD and floating-point support is configured on a per-core
basis.
Cryptographic Extension • Included
• Not included
If the Cryptographic Extension is included, then it is included on all cores
that implement Advanced SIMD and floating-point support. There is no
option to implement the Cryptographic Extension without Advanced
SIMD and floating-point support.
The following table lists the implementation options at build time for the processor.
Table A1-2 Implementation options for the processor
Feature Range of options Notes
Number of cores • 1
• 2
• 3
• 4
All cores have the same build-time configuration.
Main bus interface • AMBA 4 AXI
• AMBA 4 ACE
• AMBA 5 CHI
A1 Introduction
A1.3 Implementation options
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A1-32
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