ARM Cortex-A35 User Manual

C10.7 Performance Monitors Common Event Identification Register 0, EL0
The PMCEID0_EL0 characteristics are:
Purpose
Defines which common architectural and common microarchitectural feature events are
implemented.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
Config RO RO RO RO RO
This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.
Configurations
The PMCEID0_EL0 is architecturally mapped to:
• The AArch32 register PMCEID0. See C10.3 Performance Monitors Common Event
Identification Register 0 on page C10-695.
• The external register PMCEID0_EL0.
Attributes
PMCEID0_EL0 is a 32-bit register.
CE
31
08 716 15 12346111230 29 28 27 26 25 24 23 22 21 20 19 18 17 1314 910 5
Figure C10-5 PMCEID0_EL0 bit assignments
CE[31:0], [31:0]
Common architectural and microarchitectural feature events that can be counted by the PMU
event counters.
For each bit described in the following table, the event is implemented if the bit is set to 1, or
not implemented if the bit is set to 0.
Table C10-5 PMU common events
Bit Event number Event mnemonic Description
[31]
0x1F
L1D_CACHE_ALLOCATE
L1 Data cache allocate:
0
This event is not implemented.
[30]
0x1E
CHAIN
Chain. For odd-numbered counters, counts once for each overflow of the
preceding even-numbered counter. For even-numbered counters, does not
count:
1
This event is implemented.
[29]
0x1D
BUS_CYCLES
Bus cycle:
1
This event is implemented.
C10 PMU registers
C10.7 Performance Monitors Common Event Identification Register 0, EL0
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C10-707
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English