ARM Cortex-A35 User Manual

B2.63 AArch32 Memory Model Feature Register 0, EL1
The ID_MMFR0_EL1 characteristics are:
Purpose
Provides information about the memory model and memory management support in AArch32.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_MMFR0_EL1 is architecturally mapped to AArch32 register ID_MMFR0. See
B1.80 Memory Model Feature Register 0 on page B1-281.
Attributes
ID_MMFR0_EL1 is a 32-bit register.
31
12 11 8 7 0
OuterShr PMSA
4 328 27 24 23 20 19 16 15
FCSE AuxReg TCM ShareLvl VMSAInnerShr
Figure B2-36 ID_MMFR0_EL1 bit assignments
InnerShr, [31:28]
Indicates the innermost shareability domain implemented:
0x1 Implemented with hardware coherency support.
FCSE, [27:24]
Indicates support for Fast Context Switch Extension (FCSE):
0x0 Not supported.
AuxReg, [23:20]
Indicates support for Auxiliary registers:
0x2 Support for Auxiliary Fault Status Registers (AIFSR and ADFSR) and Auxiliary
Control Register.
TCM, [19:16]
Indicates support for TCMs and associated DMAs:
0x0 Not supported.
ShareLvl, [15:12]
Indicates the number of shareability levels implemented:
0x1 Two levels of shareability implemented.
OuterShr, [11:8]
Indicates the outermost shareability domain implemented:
0x1 Implemented with hardware coherency support.
B2 AArch64 system registers
B2.63 AArch32 Memory Model Feature Register 0, EL1
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English