B2.58 AArch32 Instruction Set Attribute Register 1, EL1
The ID_ISAR1_EL1 characteristics are:
Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_ISAR1_EL1 is architecturally mapped to AArch32 register ID_ISAR1. See
B1.75 Instruction Set Attribute Register 1 on page B1-271.
Attributes
ID_ISAR1_EL1 is a 32-bit register.
31
28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Jazelle Interwork Immediate IfThen Extend Except_AR Except Endian
Figure B2-31 ID_ISAR1_EL1 bit assignments
Jazelle, [31:28]
Indicates the implemented Jazelle state instructions:
0x1 Adds the BXJ instruction, and the J bit in the PSR. This setting might indicate a trivial
implementation of the Jazelle extension.
Interwork, [27:24]
Indicates the implemented Interworking instructions:
0x3 • The BX instruction, and the T bit in the PSR.
• The BLX instruction. The PC loads have BX-like behavior.
• Data-processing instructions in the A32 instruction set with the PC as the
destination and the S bit clear, have BX-like behavior.
Immediate, [23:20]
Indicates the implemented data-processing instructions with long immediates:
0x1 • The MOVT instruction.
• The MOV instruction encodings with zero-extended 16-bit immediates.
• The T32 ADD and SUB instruction encodings with zero-extended 12-bit immediates,
and other ADD, ADR, and SUB encodings cross-referenced by the pseudocode for
those encodings.
IfThen, [19:16]
Indicates the implemented If-Then instructions in the T32 instruction set:
0x1 The IT instructions, and the IT bits in the PSRs.
Extend, [15:12]
B2 AArch64 system registers
B2.58 AArch32 Instruction Set Attribute Register 1, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-457
Non-Confidential
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