C8.17 External Debug Component Identification Register 1
The EDCIDR1 characteristics are:
Purpose
Provides information to identify an external debug component.
Usage constraints
This register is accessible as follows:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table C1-1 Conditions on external register access to debug registers on page C1-579 describes
the condition codes.
Configurations
The EDCIDR1 is in the Debug power domain.
Attributes
See C8.1 Memory-mapped debug register summary on page C8-644.
RES0
31 0
PRMBL_1
78 34
CLASS
Figure C8-13 EDCIDR1 bit assignments
[31:8]
Reserved, RES0.
CLASS, [7:4]
0x9 Debug component.
PRMBL_1, [3:0]
0x0 Preamble.
The EDCIDR1 can be accessed through the external debug interface, offset 0xFF4.
C8 Memory-mapped debug registers
C8.17 External Debug Component Identification Register 1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C8-666
Non-Confidential
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