B2.39 Domain Access Control Register, EL2
The DACR32_EL2 characteristics are:
Purpose
Allows access to the AArch32 DACR register from AArch64 state only. Its value has no effect
on execution in AArch64 state.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
DACR32_EL2 is architecturally mapped to AArch32 register DACR (NS). See B1.47 Domain
Access Control Register on page B1-221.
Attributes
DACR32_EL2 is a 32-bit register.
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure B2-14 DACR32_EL2 bit assignments
D<n>, bits [2n+1:2n], for n = 0 to 15, [31:0]
Domain n access permission, where n = 0 to 15. Permitted values are:
0b00 No access. Any access to the domain generates a Domain fault.
0b01 Client. Accesses are checked against the permission bits in the translation tables.
0b11 Manager. Accesses are not checked against the permission bits in the translation tables.
The value 0b10 is reserved.
To access the DACR32_EL2:
MRS <Xt>, DACR32_EL2 ; Read DACR32_EL2 into Xt
MSR DACR32_EL2, <Xt> ; Write Xt to DACR32_EL2
Register access is encoded as follows:
Table B2-30 DACR32_EL2 access encoding
op0 op1 CRn CRm op2
11 100 0011 0000 000
B2 AArch64 system registers
B2.39 Domain Access Control Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-421
Non-Confidential
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