B2.96 Translation Control Register, EL3
The TCR_EL3 characteristics are:
Purpose
Controls translation table walks required for stage 1 translation of memory accesses from EL3
and holds cacheability and shareability information for the accesses.
TCR_EL3 is part of the Virtual memory control registers functional group.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW
Configurations
TCR_EL3 is mapped to AArch32 register TTBR(S). See B1.113 Translation Table Base
Register 0 on page B1-346
Attributes
TCR_EL3 is a 32-bit register.
RES0
31 30 24 23 22 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5
0
RES0SH0TG0PS
IRGN0
ORGN0
T0SZ
RES0
TBI
RES0
RES1RES1
Figure B2-67 TCR_EL3 bit assignments
[31]
Reserved, RES1.
[30:24]
Reserved, RES0.
[23]
Reserved, RES1.
[22:21]
Reserved, RES0.
TBI, [20]
Top Byte Ignored. Indicates whether the top byte of the input address is used for address match.
The possible values are:
0 Top byte used in the address calculation.
1 Top byte ignored in the address calculation.
[19]
Reserved, RES0.
PS, [18:16]
Physical address size. The possible values are:
B2 AArch64 system registers
B2.96 Translation Control Register, EL3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-543
Non-Confidential
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