ARM Cortex-A35 User Manual

B1.45 Cache Size Selection Register
The CSSELR characteristics are:
Purpose
Selects the current CCSIDR, see B1.39 Cache Size ID Register on page B1-201, by specifying:
• The required cache level.
• The cache type, either instruction or data cache.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
If the CSSELR level field is programmed to a cache level that is not implemented, then a read of
CSSELR returns an UNKNOWN value in CSSELR.Level.
Configurations
CSSELR (NS) is architecturally mapped to AArch64 register CSSELR_EL1. See B2.34 Cache
Size Selection Register, EL1 on page B2-408.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
Attributes
CSSELR is a 32-bit register.
InD
UNK/SBZP
31 4 3 1 0
Level
Figure B1-9 CSSELR bit assignments
[31:4]
Reserved, RES0.
Level, [3:1]
Cache level of required cache:
0b000 L1.
0b001 L2.
0b010-0b111 Reserved.
The combination of Level=0b001 and InD=1 is reserved.
InD, [0]
Instruction not Data bit:
0 Data or unified cache.
1 Instruction cache.
The combination of Level=0b001 and InD=1 is reserved.
B1 AArch32 system registers
B1.45 Cache Size Selection Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English