B1.74 Instruction Set Attribute Register 0
The ID_ISAR0 characteristics are:
Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, and ID_ISAR5. See:
• B1.75 Instruction Set Attribute Register 1 on page B1-271
• B1.76 Instruction Set Attribute Register 2 on page B1-273
• B1.77 Instruction Set Attribute Register 3 on page B1-275
• B1.78 Instruction Set Attribute Register 4 on page B1-277
• B1.79 Instruction Set Attribute Register 5 on page B1-279
Configurations
ID_ISAR0 is architecturally mapped to AArch64 register ID_ISAR0_EL1. See B2.57 AArch32
Instruction Set Attribute Register 0, EL1 on page B2-455.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_ISAR0 is a 32-bit register.
31
28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
RES0 Divide Debug Coproc CmpBranch Bitfield BitCount Swap
Figure B1-29 ID_ISAR0 bit assignments
[31:28]
Reserved, RES0.
Divide, [27:24]
Indicates the implemented Divide instructions:
0x2 • SDIV and UDIV in the T32 instruction set.
• SDIV and UDIV in the A32 instruction set.
Debug, [23:20]
Indicates the implemented Debug instructions:
0x1 BKPT.
Coproc, [19:16]
Indicates the implemented Coprocessor instructions:
0x0 None implemented, except for separately attributed by the architecture including
CP15, CP14, Advanced SIMD and floating-point.
CmpBranch, [15:12]
B1 AArch32 system registers
B1.74 Instruction Set Attribute Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-269
Non-Confidential
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