ARM Cortex-A35 User Manual

C10.11 Performance Monitors Peripheral Identification Registers
The Performance Monitors Peripheral Identification Registers provide standard information required for
all components that conform to the Arm PMUv3 architecture.
The following table lists the Performance Monitors Peripheral Identification Registers.
Table C10-8 Summary of the Performance Monitors Peripheral Identification Registers
Register Value Offset
Peripheral ID4
0x04 0xFD0
Peripheral ID5
0x00 0xFD4
Peripheral ID6
0x00 0xFD8
Peripheral ID7
0x00 0xFDC
Peripheral ID0
0xDA 0xFE0
Peripheral ID1
0xB9 0xFE4
Peripheral ID2
0x3B 0xFE8
Peripheral ID3
0x00 0xFEC
Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight
Peripheral ID Registers define a single 64-bit Peripheral ID.
C10 PMU registers
C10.11 Performance Monitors Peripheral Identification Registers
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English