ARM Cortex-A35 User Manual

C5.5 Encoding for walk cache
The following table shows the data fields in the walk cache descriptor.
Table C5-11 Walk cache descriptor fields
Bits Name Description
[115:113] Parity bits If CPU cache protection is not implemented, these bits are absent.
[112:83] PA Physical Address of the second, last, translation level.
[82:60] VA Virtual address.
[59] VA sign Virtual address sign bit.
[58:55] - Reserved, must be zero.
[54:39] ASID Address Space Identifier.
[38:31] VMID Virtual Machine Identifier.
[30] NS, walk Security state that the entry was fetched in.
[29:23] - Reserved, must be zero.
[22:19] Domain Valid only if the entry was fetched in VMSAv7 format.
[18:16] Entry size
Memory size to which entry maps:
0b100
1MB.
0b101
2MB.
0b010
8MB.
0b110, 0b011
32MB.
0b001
128MB.
0b111
512MB.
[15] NSTable Combined NSTable bits from first and second-level stage 1 tables or NS descriptor (VMSA).
[14] PXNTable Combined PXNTable bits from stage1 descriptors up to last level.
[13] XNTable Combined XNTable bit from stage1 descriptors up to last level.
[12:11] APTable Combined APTable bits from stage1 descriptors up to last level.
[10]
EL3 Set if the entry was fetched in AArch64 EL3 mode.
[9] EL2 Set if the entry was fetched in EL2 mode.
[8:1] Attrs Physical attributes of the final level stage 1 table.
[0] Valid
Valid bit:
0
Entry does not contain valid data.
1
Entry contains valid data.
C5 Direct access to internal memory
C5.5 Encoding for walk cache
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English