ARM Cortex-A35

Table C5-10 TLB encoding for memory types and shareability (continued)
Bits Memory type Description
[3:2] Device
Device type:
00
nGnRnE.
01
nGnRE.
10
nGRE.
11
GRE.
Non-coherent, Outer WB
Non-coherent, Outer WT
Coherent, Inner WB and Outer WB
Outer allocation hint:
00
NA.
01
WA.
10
RA.
11
WRA.
Non-coherent, Outer NC
Inner type:
00
NC.
01
WB.
10
WT.
11
Unused.
[1:0]
Device
Non-coherent, Outer WB
Non-coherent, Outer NC
Non-coherent, Outer WT
Coherent, Inner WB and Outer WB
Shareability:
00
Non-shareable.
01
Unused.
10
Outer shareable.
11
Inner shareable.
Related information
C5.5 Encoding for walk cache on page C5-617
C5.6 Encoding for IPA cache on page C5-618
C5.1 About direct access to internal memory on page C5-608
C5 Direct access to internal memory
C5.4 Encoding for the main TLB RAM
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C5-616
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