B2.86 Revision ID Register, EL1
The REVIDR_EL1 characteristics are:
Purpose
Provides implementation-specific minor revision information that can be interpreted only in
conjunction with the Main ID Register.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
REVIDR_EL1 is architecturally mapped to AArch32 register REVIDR. See B1.102 Revision ID
Register on page B1-325.
Attributes
REVIDR_EL1 is a 32-bit register.
31
0
ID number
Figure B2-57 REVIDR_EL1 bit assignments
ID number, [31:0]
Implementation-specific revision information. The reset value is determined by the specific
Cortex‑A35 processor implementation.
0x00000000 Revision code is zero.
To access the REVIDR_EL1:
MRS <Xt>, REVIDR_EL1 ; Read REVIDR_EL1 into Xt
Register access is encoded as follows:
Table B2-80 REVIDR_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0000 110
B2 AArch64 system registers
B2.86 Revision ID Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-518
Non-Confidential
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