C11.40 Single-Shot Comparator Status Register 0
The TRCSSCSR0 characteristics are:
Purpose
Indicates the status of the single-shot comparator. TRCSSCSR0 is sensitive to instruction
addresses.
Usage constraints
• Accepts writes only when the trace unit is disabled.
• The STATUS bit value is stable only when TRCSTATR.PMSTABLE==1.
Configurations
Available in all configurations.
Attributes
See C11.1 ETM register summary on page C11-733.
31 30 3 2 1 0
RES0
STATUS DV
DA
INST
Figure C11-39 TRCSSCSR0 bit assignments
STATUS, [31]
Single-shot status. This indicates whether any of the selected comparators have matched:
0 Match has not occurred.
1 Match has occurred at least once.
When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be
explicitly written to 0 to enable this single-shot comparator control.
[30:3]
Reserved, RES0.
DV, [2]
Data value comparator support:
0 Single-shot data value comparisons not supported.
DA, [1]
Data address comparator support:
0 Single-shot data address comparisons not supported.
INST, [0]
Instruction address comparator support:
1 Single-shot instruction address comparisons supported.
The TRCSSCSR0 can be accessed through the external debug interface, offset 0x2A0.
C11 ETM registers
C11.40 Single-Shot Comparator Status Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C11-786
Non-Confidential
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