B1.1 AArch32 register summary
In AArch32 state, you access the system registers through a conceptual coprocessor, identified as CP15,
the System Control Coprocessor.
Within CP15, there is a top-level grouping of system registers by a primary coprocessor register number,
c0-c15. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information about using the conceptual System Control Coprocessor in a VMSA context.
The system register space includes System operations system registers and System operations. The
description of the system register space describes the permitted access, RO, WO, or RW, to each register
or operation.
The following sections describe the CP15 system control registers grouped by CRn order, and are
accessed by the MCR and MRC instructions.
• B1.2 c0 registers on page B1-152.
• B1.3 c1 registers on page B1-155.
• B1.4 c2 registers on page B1-156.
• B1.5 c3 registers on page B1-157.
• B1.6 c4 registers on page B1-158.
• B1.7 c5 registers on page B1-159.
• B1.8 c6 registers on page B1-160.
• B1.9 c7 registers on page B1-161.
• B1.10 c7 system operations on page B1-162.
• B1.11 c8 system operations on page B1-165.
• B1.12 c9 registers on page B1-167.
• B1.13 c10 registers on page B1-168.
• B1.14 c11 registers on page B1-169.
• B1.15 c12 registers on page B1-170.
• B1.16 c13 registers on page B1-172.
• B1.17 c14 registers on page B1-173.
• B1.18 c15 registers on page B1-174.
The following subsection describes the 64-bit registers and provides cross-references to individual
register descriptions:
• B1.19 64-bit registers on page B1-175.
In addition to listing the CP15 system registers by CRn ordering, the following subsections describe the
CP15 system registers by functional group:
• B1.20 AArch32 Identification registers on page B1-176.
• B1.21 AArch32 Virtual memory control registers on page B1-178.
• B1.22 AArch32 Fault handling registers on page B1-179.
• B1.23 AArch32 Other System control registers on page B1-180.
• B1.24 AArch32 Address registers on page B1-181.
• B1.25 AArch32 Thread registers on page B1-182.
• B1.26 AArch32 Performance monitor registers on page B1-183.
• B1.27 AArch32 Secure registers on page B1-185.
• B1.28 AArch32 Virtualization registers on page B1-186.
• B1.29 AArch32 GIC system registers on page B1-188.
• B1.30 AArch32 Generic Timer registers on page B1-190.
• B1.31 AArch32 Implementation defined registers on page B1-191.
The following table describes the column headings in the CP15 register summary tables used throughout
this section.
B1 AArch32 system registers
B1.1 AArch32 register summary
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
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